Back gate biasing is a powerful method for adaptive power management. Planar fully depleted silicon-on-insulator (FDSOI) devices with thin buried oxide (BOX) are especially of interest because they provide significant body factor without compromising device performance. Body factor (γ) is a ratio of the shift in the threshold voltage (Vt) to the change in the back gate bias (BG), i.e., γ=ΔVt/ΔV_BG. For back gate biasing to be area efficient, a group of transistors with the same polarity and target threshold voltage should share a single back gate. However, the back gate should be separated (isolated) from adjacent transistors that have a different polarity or need a different back bias.
The conventional method to address shared versus isolated back gates is to use deep trench isolation and rely on triple-well (junction) isolation. This way, adjacent devices with the same back gate polarity (for example n-well) share the same back gate while adjacent devices with different well polarity are isolated. This method, however, is not well-suited for future technology nodes because it 1) requires deep isolation which complicates the process and limits device packing, 2) junction isolation has a lower limit on well-to-well junction leakage especially when bias is applied, and 3) well polarity is dictated by the isolation needs (adjacent devices that require different bias cannot have the same well polarity). With regard to the second point, a given well doping is needed to meet well resistance targets, thus well-to-well junction leakage cannot be lowered below a certain limit. This also limits the options for well bias, i.e., no forward biased p-n junction is allowed.
To remove these restrictions from back gate designs, a dual depth isolation is needed. In this approach, devices that share the same back gate are isolated by a shallow trench that extends only through a top channel layer but does not penetrate through the BOX, whereas devices that have different back gate polarity are isolated by a deeper trench. With a double-BOX structure, dual depth isolation is the only option.
There are two ways to obtain dual depth isolation. The first approach is to use two different masks to define the two (deep and shallow) isolation regions. As such, the deep and shallow trenches will not be self-aligned. This approach also creates non-uniform depth at the intercepts of the shallow and deep trenches. Therefore, the application of this first approach for dense arrays like static random access memory (SRAM) is very challenging. The second approach is to use integration schemes to produce different depth trenches with a single mask. The most common approach is to rely on the trench opening to obtain trenches with different depth (e.g., by using loading effects in reactive ion etching (RIE) processes, wherein trenches that have a wider opening are etched deeper than trenches that are narrower). The main disadvantage of this approach is the area penalty. For example, with an SRAM array with 40 nanometer (nm) ground role (GR)-limited spacing between adjacent transistors, spacing of about 80 nm is needed between n-channel field effect transistors (NFETs) and p-channel field effect transistors (PFETs) to ensure reasonable difference in trench depth.
Therefore, dual depth isolation techniques that solve the above-described problems would be desirable.